The present disclosure relates to a protection element serving as a countermeasure against ESDs (Electro-Static Discharges) and a semiconductor device provided with the protection element.
As protection elements each serving as a countermeasure against ESDs, there are known a GGMOS (Gate Grounded MOS), a thyristor and an RC timer, to mention a few.
These protection elements are properly used in their respective applications. The GGMOS has a simple structure so that the GGMOS has been used for the longest period of time among these protection elements.
A typical structure of the GGMOS is shown in FIG. 7. FIG. 7 is a diagram showing a GGMOS device of the NMOS type. As shown in the figure, the GGMOS employs a PWell area 51, a source area 52, a drain area 53, a gate insulation film 54 and a gate 55.
As shown in FIG. 7, in comparison with an ordinary MOS transistor having the same structure, in the structure of the GGMOS, the gate 55 is shorted to the source area 52 and both are connected to the ground GND or the electric potential of the ground.
In the structure of the GGMOS, for a surge input coming from the drain, till an input voltage V represented by the horizontal axis attains a certain voltage level denoted by notation Vt1, the GGMOS does not work as shown in FIG. 8. That is to say, till the input voltage V attains the voltage level Vt1, a current I represented by the vertical axis does not flow. As the input voltage V attains the voltage level Vt1, a bipolar operation is started and the input voltage V drops so that the current I having a large magnitude flows.
In the ESD protection element having the related-art GGMOS structure, however, the voltage Vt1 has a specific value due to the GGMOS peculiar configuration such as the gate length and impurity concentrations in a variety of areas including the Well, the source and the drain.
Thus, depending on the application, in order to control the voltage Vt1 to a desired level, it is necessary to change the configuration of the protection element.
For raising the voltage Vt1, there are relatively simple methods such as increasing the gate length.
For reducing the voltage Vt1, there are known the following 3 methods:
(1) a method of changing the configuration of the protection element to an impurity configuration with a low withstanding voltage;
(2) a method of setting the electric potential of the Well area at a floated level; and
(3) a method of providing a circuit for controlling the gate voltage (refer to M. G. Khazhinskyet al., “Engineering Single NMOS and PMOS Output Buffers for Maximum Failure Voltage in Advanced CMOS technologies,” EOS/ESD Symposium 2004, for example, referred to as Non-Patent Document 1 hereinafter).
As described in Non-Patent Document 1, changes of the voltage Vt1 caused by variations of the gate voltage are used as shown in FIG. 9. In addition, a circuit for controlling the gate voltage is provided at an input stage. This circuit detects a surge current and carries out control so that the gate voltage of the protection element becomes equal to the drain voltage.
Thus, in FIG. 9, Vgs=Vds. As a result, in comparison with the related-art configuration in which Vgs=0 V, the voltage Vt1 can be lowered.